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Functional Verification Engineer (m/f) ASIC

Munich December 18th, 2017


Due to the growth of our ALTEN Germany headquarter, we release this invitation for Functional Verification Engineer (m/f) ASIC to join our team in Munich. Below you will find the main objective of the position and the requirements you must possess in order to start the selection process!

We are looking forward to speak with you in order to understand more in detail your expectations and ambitions!


  • As Functional Verification Engineer (m/f) ASIC you are responsible for developing a suitable verification environment in the semiconductor industry
  • You review functional specifications and create the verification strategy by using varied methodologies
  • Furthermore, you support the debugging and develop test scenarios
  • Subsequently, you are responsible for the documentation of your results
  • In all this, you work proactively in an international team


  • You have a Bachelor/ Master degree in Electrical Engineering, Electronics, or comparable
  • You are experienced with a a high level verification language like SystemVerilog and/or Specman
  • Furthermore, you have a profound understanding of OVM, UVM or eUVM methodologies
  • In addition, you possess good skills in VHDL or Verilog and design basics
  • You have a good understanding of C++ or a similar programming language and scripting experience with Perl
  • Fluent English and good German skills complete your profile